Computer technology is reaching the point where a host computer system, such as a workstation, will be able to produce or consume data at close to 1 Gbps. High speed telecommunications networks (such as the Broadband-Integrated Digital Services Network (B-ISDN)) capable of transporting data at that speed are also becoming available. However, a major bottleneck exists at the interface between the host computer and the network. Two main functions are performed at this point:
1. data is converted between a format useful to the host computer and the format that is required by the network;
2. data is moved between the host computer's memory and the network. See copending application Ser. No. 660,637, filed Feb. 25, 1991.
The amount of processing power required to perform those functions at a speed sufficient to load a Gbps network is unavailable in most computers. Previous approaches to solving this problem employ front-end "protocol engines" to off-load some of the processing from the host computer. See e.g., E. A. Arnould, et al., "The Design of Nectar: A Network Backplane for a Heterogeneous Multi-computer," Technical Report CMU-CS-89-101, Computer Science Dept., CMU, (January, 1989); R. Reach, "Ultranet: An Architecture for Gigabit Networking." Local Computer Networks, pp. 232-248, Minneapolis, Minn., (October, 1990); H. Kanakia and D. Cheriton, "The VMP Network Adapter Board (NAB): High-performance Network Communication for Multiprocessors," Proc. ACM SIGCOMM '88, pp. 175-187, Stanford, Cal. (August 1988); H. Kanakia, "High Performance Host Interfacing for Packet Switched Networks," Ph.D. thesis, Stanford University, (November, 1989); G. Chesson "XTP/PE Overview," Proc. 13th Con. on Local Computer Networks, pp. 292-296, Minneapolis, Minn., (October, 1988). In addition, previous approaches to this problem are based on very large packet sizes (1 Kbyte to 32 Kbytes), thus those approaches are not suitable for use with a telecommunications network that utilizes the Asynchronous Transfer Mode (ATM) transmission technique.
According to the ATM technique, data is transmitted in 53-byte packets called cells. With 53-byte cells, headers must be generated and processed at a far more rapid rate than when packets are 1-32 Kbytes. The prior art approaches to interfacing a host computer to a telecommunications network at gigabit speeds do not process headers fast enough to be useful to interface a computer with an ATM network.
The ATM is a transmission technique for transmitting data belonging to a variety of applications across a network. An important advantage of the ATM technique is that it provides a single transmission format by which data from a variety of network element sources (such as voice, high definition video, and computer and terminal connections) may be transmitted in a single transmission format, rather than requiring separate transmission formats and processing facilities for each type of data.
Each 53-byte ATM cell comprises 48 bytes of payload and a 5-byte ATM header. The header includes a Virtual Channel Identifier (VCI) that indicates the particular channel or connection to which the cell belongs; it is used to direct the cell at the various switching points in the network. The ATM cell header also includes a Cyclic Redundancy Check (CRC) byte. The 48-byte payload may also contain a 4-byte Adaptation Layer header the contents of which depend on the application.
The ATM cells are transmitted in slots defined in the payload fields of, e.g., the frames of the SONET STS-3c signal (155 Mbps) or the SONET STS-12 signal (622 Mbps), which may be formed by multiplexing four STS-3c signals. An OC-48 optical signal may be used to achieve transmission rates of over 2 Gbps.
The ATM technique is referred to as being asynchronous because the slots in the frames of the signals are not reserved for the cells of particular applications, but instead are filled by the cells of various applications in accordance with the various applications' current demand for slots and the current availability of slots. The ATM transmission technique is expected to be the standard for providing broadband telecommunications services through a broadband trunk and exchange network such as the B-ISDN.
As mentioned above, the interface between a host computer and the network presents a severe bottleneck when attempting to move data at Gbps speeds. Interface (or protocol) architectures can be viewed as a stack of layers. The ISO OSI model, for example, consists of seven layers. The "highest" layer, the application layer, is the application program interface (API) to the network. The physical layer is the hardware that connects the node to the network medium. The intervening layers perform additional functions, such as reliable delivery, connection management, etc., as required by the API. See, e.g., A. Tannenbaum, Computer Networks.
There are several research projects directed to providing high-performance host interfaces. The major difference between the respective implementations of the projects is the number of protocol processing functions performed by the host interface. One important focal point has been the development of interfaces that accelerate transport protocol processing. See M. Zitterbart, "High-Speed Transport Components," IEEE Network, pp. 54-63 (January, 1991).
Kanakia and Cheriton's VMP Network Adapter Board serves as a hardware implementation of Cheriton's Versatile Message Transaction Protocol (VMTP). See H. Kanakia and D. Cheriton, "The VMP Network Adapter Board (NAB): High Performance Network Communication for Multiprocessors," Proceedings, SIGMETRICS '88 (1988).
Abu-Amara et al. are capable of targeting any set of protocol layers (to the degree that they can be precisely specified) with their PSi silicon compiler approach. With that method, the protocol is specified using a symbolic programming language and mask descriptions for fabrication process layers are generated as output of a compiler. The masks are then used to create custom hardware. See H. Abu-Amara, et al., "PSi: A Silicon Compiler for Very Fast Protocol Processing," Protocols for High Speed Networks, ed. R. C. Williamson, North-Holland (1989).
The Nectar Communications Accelerator Board (CAB) may be programmed with various protocols. The CAB communicates with the host memory directly and the programmability can conceivably be used by applications to customize protocol processing. See E. A. Arnould, et al., "The Design of Nectar: A Network Backplane for Heterogeneous Multicomputers," Proceedings, ASPLOS-III pp. 205-216 (April, 1987).
Cooper et al. have reported that TCP/IP and a number of Nectar-specific protocols have been implemented on the CAB connected to Sun-4 processors. See E. Cooper, et al., "Protocol Implementation on the Nectar Communication Processor," Proceedings, SIGCOMM '90, Philadelphia, Pa. pp. 135-144 (Sep. 24-27, 1990).
Davie of Bellcore has reported on a host interface designed for the TurboChannel bus of the Dec Station 5000 workstation. That design relies on an Intel 80960 RISC microController to perform the protocol processing and flow control for a trunk group of four STS-3c lines (622 Mbps). See B. S. Davie, "Host Interface Design for Experimental, Very High Speed Networks," Proc. Compcon Spring '90, San Francisco, Cal. pp. 102-106 (February 1990); B. S. Davie, "A Host-Network Interface Architecture for ATM," Proceedings, SIGCOMM 1991, Zurich, Switzerland (Sep. 4-6, 1991).
The IBM RS/6000 workstation is one example of a host computer for which an interface in accordance with the present invention is suitable. The RS/6000 workstation has a 32-bit MicroChannel bus for I/O interconnections. Transfers may be either 8, 16, or 32 bits wide. The basic cycle time for the bus is 200 ns, but with data streaming a single 100 ns setup time may be amortized over many transfers. The streaming operation starts out as a basic transfer cycle. After the transfer has been set up, the slave acknowledges that it may support a streaming transaction, which enables the master to then start the 10 Mhz streaming strobe. A data transfer may then be made every 100 ns. No addressing information is generated by the master while the stream is in progress. Streaming may be terminated or paused by either the slave or the master. See H. B. Bakoglu, et al., "The IBM RISC System/6000 Processor: Hardware Overview," IBM Journal of Research and Development 34(1), pp. 12-22 (January, 1990).
A goal of the present invention is to provide an interface between a network element and a telecommunications network that operates at near Gbps speeds and that is compatible for use with the ATM transmission technique. A further goal of the present invention is to provide an interface that is capable of receiving data from a network element, such as a host computer, and segmenting it into ATM cells for transmission over a telecommunications network. A still further goal of the present invention is to provide an interface that is capable of receiving and reassembling segmented ATM data for use by the network element. A yet further goal of the present invention is to provide a high-performance interface for an IBM/6000 workstation host in an ATM telecommunications network.